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74ACT818 - 74ACT818
74ACT818 8-Bit Diagnostic Register
July 1988 Revised January 1999
74ACT818 8-Bit Diagnostic Register
ACT818 high-speed, general-purpose pipeline register with on-board diagnostic register performing serial diagnostics and/or writable control store loading. D-to-Y path provides 8-bit parallel data path pipeline register normal system operation. diagnostic register load parallel data from pipeline register output data through input port loading). 8-bit diagnostic register multiplexer inputs that select parallel inputs from Y-port adjacent bits diagnostic register operate right-shift-only register. This register then participate serial loop throughout system where normal data, address, status control registers replaced with ACT818 diagnostic pipeline registers. loop used scan complete test routine starting point (Data, Address, etc.). Then after specified number machine cycles scans results inspected expected results. loading accomplished using same technique. instruction word serially shifted into shadow register written into enabling output.
Features
On-line off-line system diagnostics Swaps contents diagnostic register output register Diagnostic register diagnostic testing Cascadable wide control words used microprogramming Edge-triggered registers Outputs source/sink ACT818 TTL-compatible inputs ACT818 functionally- pin-compatible Am29818 74S818
Applications
Register microprogram control store Status register Data register Instruction register Interrupt mask register Pipeline register General purpose register Parallel-serial/serial-parallel converter
Ordering Code:
Order Number 74ACT818SPC Order Package N24C Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300" Wide
Logic Symbol
Connection Diagram
Assignment
FACTis trademark Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation
DS009801.prf
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74ACT818
Descriptions
Names D0-D7 DCLK MODE PCLK Y0-Y7 Description Data Inputs Serial Data Input Diagnostics Clock Control Input Pipeline Register Clock Output Enable Input Serial Data Output Data Outputs
Functional Description
Data transfers into diagnostic register occur LOW-to-HIGH transition DCLK. Mode determine what data source will loaded. pipeline register loaded LOW-to-HIGH transition PCLK. Mode selects whether data source data input diagnostic register output. Because independence clock inputs, data shifted diagnostic register DCLK loaded into pipeline register from data input PCLK simultaneously, long setup hold times violated. This simultaneous operation legal.
Function Table
Inputs MODE DCLK PCLK Outputs Diagnostic Reg. SI<SI SO<SDI SI<YI Hold PI<DI PI<SI Normal Load Pipeline Register Load Diagnostic Register from Disabled Load Pipeline Register from Diagnostic Register Hold Diagnostic Register; Enabled Pipeline Reg. Serial Shift; D7-D0 Disabled Operation
HIGH Voltage Level Voltage Level Immaterial
LOW-to-HIGH Clock Transition
Diagnostic Register
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74ACT818
Block Diagram
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74ACT818
Absolute Maximum Ratings(Note
Supply Voltage (VCC) Input Diode Current (IIK) -0.5V +0.5V Input Voltage (VI) Output Diode Current (IOK) -0.5V 0.5V Output Voltage (VO) Output Source Sink Current (IO) Ground Current Output IGND) Storage Temperature (TSTG) -65°C +150°C -0.5V 0.5V -0.5V +0.5V -0.5V +7.0V
Junction Temperature (TJ) PDIP 140°C
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) from 0.8V 2.0V 4.5V, 5.5V
Note Absolute maximum ratings those values beyond which damage device occur. databook specifications should met, without exception, ensure that system design reliable over power supply, temperature, output/input loading variables. Fairchild does recommend operation FACTcircuits outside databook specifications.
4.5V 5.5V -40°C +85°C mV/ns
Electrical Characteristics
Symbol Parameter Minimum HIGH Level Input Voltage Maximum Level Input Voltage Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum Quiescent Supply Current ICCT Maximum Additional ICC/Input Minimum HIGH Level Output Voltage, Y0-Y7 Outputs Minimum HIGH Level Output Voltage, D0-D7, Outputs Maximum Level Output Voltage, Y0-Y7 Outputs Maximum Level Output Voltage, D0-D7, Outputs IOLD Minimum Dynamic Output Current Y0-Y7 Outputs IOHD Minimum Dynamic Output Current Y0-Y7 Outputs VOHD 3.85V 0.36 0.36 0.36 0.36 0.44 0.44 0.44 0.44 3.86 4.86 3.76 4.76 (Note VOLD 1.65V 3.86 4.86 3.76 4.76 2.1V 5.5V =-24 (Note 80.0 VOUT +25°C -40°C +85°C Guaranteed Limits VOUT 0.1V 0.1V VOUT 0.1V 0.1V Units Conditions
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74ACT818
Electrical Characteristics
Symbol IOLD Parameter Minimum Dynamic Output Current D0-D7, Outputs (Note IOHD Minimum Dynamic Output Current D0-D7, Outputs (Note
(Continued)
+25°C -40°C +85°C Guaranteed Limits VOLD 1.65V
Units
Conditions
VOHD 3.85V
Note outputs loaded; thresholds input associated with output under test. Note Test load ground.
Electrical Characteristics
Symbol Parameter (Note tPHL Propagation Delay PCLK tPLH Propagation Delay PCLK tPHL Propagation Delay MODE tPLH Propagation Delay MODE tPHL Propagation Delay tPLH Propagation Delay tPHL Propagation Delay DCLK tPLH Propagation Delay DCLK tPZL Output Enable Time tPLZ Output Disable Time tPZL Output Enable Time DCLK tPLZ Output Disable Time DCLK tPZH Output Enable Time tPHZ Output Disable Time tPZH Output Enable Time DCLK tPHZ Output Disable Time DCLK
Note Voltage Range 5.0V ±0.5V.
+25°C
-40°C +85°C Units
10.0
11.0
12.0
11.5
12.5
10.5
12.0
10.5
12.0
12.5
14.0
13.0
14.5
10.0
12.0
13.5
11.0
12.0
10.0
11.0
11.0
11.5
11.5
13.0
12.0
13.0
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74ACT818
Operating Requirements
Symbol Setup Time PCLK Hold Time PCLK Setup Time MODE PCLK Hold Time MODE PCLK Setup Time DCLK Hold Time DCLK Setup Time MODE DCLK Hold Time MODE DCLK Setup Time DCLK Hold Time DCLK Setup Time DCLK PCLK Setup Time PCLK DCLK Pulse Width PCLK HIGH Pulse Width DCLK HIGH
Note Voltage range 5.0V 0.5V.
+25°C -1.0 -0.5 -0.5 11.0
-40°C +85°C Guaranteed Minimum 10.5 11.5 Units
Parameter
(Note
Capacitance
Symbol Parameter Input Capacitance Power Dissipation Capacitance Units OPEN 5.0V Conditions
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74ACT818 8-Bit Diagnostic Register
Physical Dimensions inches (millimeters) unless otherwise noted
Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300" Wide Package Number N24C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: critical component component life support Life support devices systems devices systems device system whose failure perform reawhich, intended surgical implant into sonably expected cause failure life support body, support sustain life, whose failure device system, affect safety effectiveness. perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury www.fairchildsemi.com user.
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.
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