74AC125 74ACT125
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74AC125 - 74AC125
74ACT125 - 74ACT125
74AC125 74ACT125 Quad Buffer with 3-STATE Outputs
March 1990 Revised November 1999
74AC125 74ACT125 Quad Buffer with 3-STATE Outputs
AC/ACT125 contains four independent non-inverting buffers with 3-STATE outputs.
Features
reduced Outputs source/sink ACT125 TTL-compatible outputs
Ordering Code:
Order Number 74AC125SC 74AC125SJ 74AC125MTC 74AC125PC 74ACT125SC 74ACT125SJ 74ACT125MTC 74ACT125PC Package Number M14A M14D MTC14 N14A M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available Tape Reel. Specify appending suffix letter ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Descriptions
Names Description Inputs Outputs
Function Table
Inputs
HIGH Voltage Level Voltage Level HIGH Impedance Immaterial
Output
FACT trademark Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation
DS010692
www.fairchildsemi.com
74AC125 74ACT125
Absolute Maximum Ratings(Note
Supply Voltage (VCC) Input Diode Current (IK) -0.5V 0.5V Input Voltage (VI) Output Diode Current (IOK) -0.5V 0.5V Output Voltage (VO) Output Source Sink Current (IO) Ground Current Output (ICC IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140°C -65°C +150°C -0.5V 0.5V -0.5V 0.5V -0.5V +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) Devices from 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) Devices from 0.8V 2.0V 4.5V, 5.5V 2.0V 6.0V 4.5V 5.5V -40°C +85°C
mV/ns
mV/ns
Note Absolute maximum ratings those values beyond which damage device occur. databook specifications should met, without exception, ensure that system design reliable over power supply, temperature, output/input loading variables. Fairchild does recommend operation FACT circuits outside databook specifications.
Electrical Characteristics
Symbol Parameter Minimum HIGH Level Input Voltage Maximum Level Input Voltage Minimum HIGH Level Output Voltage Maximum Level Output Voltage (Note Maximum Input Leakage Current Maximum 3-STATE Current IOLD IOHD Minimum Dynamic Output Current (Note 0.25 40.0 0.002 0.001 0.001 +25°C 2.25 2.75 2.25 2.75 2.99 4.49 5.49 3.15 3.85 1.35 1.65 2.56 3.86 4.86 0.36 0.36 0.36 -40°C +85°C Guaranteed Limits 3.15 3.85 1.35 1.65 2.46 3.76 4.76 0.44 0.44 0.44 (Note VCC, (OE) VIL, VCC, VGND VCC, VOLD 1.65V VOHD 3.85V IOUT (Note IOUT VOUT 0.1V 0.1V Units Conditions VOUT 0.1V 0.1V
(Note Maximum Quiescent Supply Current
Note outputs loaded; thresholds input associated with output under test. Note Maximum test duration output loaded time. Note Note: ICC@ 3.0V guaranteed less than equal respective limit 5.5V VCC.
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74AC125 74ACT125
Electrical Characteristics
Symbol Parameter Minimum HIGH Level Input Voltage Maximum Level Input Voltage Minimum HIGH Level Output Voltage Maximum Level Output Voltage ICCT IOLD IOHD Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current (Note Maximum Quiescent Supply Current 0.001 0.001 +25°C 4.49 5.49 3.86 4.86 0.36 0.36 ±0.1 ±0.5 -40°C +85°C Guaranteed Limits 3.76 4.76 0.44 0.44 ±1.0 ±5.0 40.0 Units Conditions VOUT 0.1V 0.1V VOUT 0.1V 0.1V IOUT (Note IOUT (Note VCC, VIL, VCC, 2.1V (Note VOLD 1.65V VOHD 3.85V
Note outputs loaded; thresholds input associated with output under test. Note Maximum test duration output loaded time. Note measured JEDEC Alternate Method.
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74AC125 74ACT125
Electrical Characteristics
Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Data Output Propagation Delay Data Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time (Note
Note Voltage Range 3.3V 0.3V Voltage Range 5.0V 0.5V
+25°C 10.5 10.0 10.0 10.5
-40°C +85°C 10.0 10.0 11.0 11.0 10.5 11.5 Units
Electrical Characteristics
Symbol Parameter (Note tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data Output Propagation Delay Data Output Output Enable Time Output Enable Time Output Disable Time Output Disable Time +25°C 10.0 -40°C +85°C 10.0 10.0 10.5 10.5 10.5 Units
Note Voltage Range 5.0V 0.5V
Capacitance
Symbol Parameter Input Capacitance Power Dissipation Capacitance AC/ACT 45.0 OPEN 5.0V Units Conditions
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74AC125 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body Package Number M14A
www.fairchildsemi.com
74AC125 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide Package Number M14D
www.fairchildsemi.com
74AC125 74ACT125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
www.fairchildsemi.com
74AC125 74ACT125 Quad Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. www.fairchildsemi.com critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com
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